1. Field of the Invention
The present invention relates to a differential amplifier circuit in a silicon-on-insulator (SOT) device.
2. Description of the Related Art
A conventional differential amplifier has a well-known configuration comprising an amplifier section 10, an output section 20, and a bias section 30 as shown in FIG. 1. The amplifier section 10 includes a pair of n-channel metal-oxide-semiconductor field-effect transistors (referred to below as NMOS transistors) 11a, 11b with sources connected to a node N1 and gates that receive respective differential input signals INP, INM. Node N1 is connected to ground (GND) through an NMOS transistor 12 that receives a bias potential BL at its gate. The drains of NMOS transistors 11a, 11b are connected to respective nodes N3, N2, which are connected to the power supply potential (VDD) through respective p-channel metal-oxide-semiconductor (PMOS) transistors 13a, 13b. The gates of PMOS transistors 13a, 13b are both connected to node N2. Node N3 is also connected to VDD through another PMOS transistor 14, which receives an enable signal EN at its gate.
The output section 20 includes a PMOS transistor 21 and a resistor 22. PMOS transistor 21 has its source connected to VDD, its gate connected to node N3 in the amplifier section 10A, and its drain connected to ground through the resistor 22. The output signal (OUT) of the differential amplifier is taken from the drain of PMOS transistor 21.
The bias section 30 receives the enable signal EN and, when the enable signal EN is active (high), holds the bias potential BL at a level such that NMOS transistor 12 conducts a predetermined current to ground.
To raise their withstand voltage, NMOS transistors 11a, 11b and PMOS transistors 13a, 13b in the amplifier section 10 and PMOS transistor 21 in the output section 20 are source-tied transistors, meaning that their respective substrate potentials are tied to their source potentials. The reason for this is that in an SOI device, the substrate is a thin silicon layer formed on an insulator such as glass. Accordingly, the body (the region between the source and drain regions) of an SOT transistor, differing from the body of a transistor formed on a conventional bulk silicon semiconductor substrate, is electrically isolated. If a large flow of current passes between the source and drain, hot carriers (electrons or holes) moving into the body may electrically charge the body until finally latch-up occurs. To prevent latch-up, in an NMOS transistor, for example, part of the junction between the N+ source region and the P-type body is a P+ region that is connected to the source region so that the body can discharge. A transistor having this configuration is referred to as a source-tied transistor.
Other methods of preventing floating substrate effects in SOI transistors are disclosed in Japanese Patent Application Publications No. H8-213564, H9-45883, and 2001-23376.
Next, the operation of the conventional differential amplifier circuit will be described.
In the standby state, in which the enable signal EN is inactive (low), the bias section 30 is deactivated and the bias potential BL drops to the ground level. The amplifier section 10 accordingly suspends operation and does not conduct any current to ground. PMOS transistor 14 is switched on, and pulls the signal SN3 at node N3 up to the VDD level. PMOS transistor 21 in the output section 20 is accordingly switched off, and the output signal (OUT) is at the ground level.
When the enable signal EN goes high, the bias section 30 starts operating, supplying the bias potential BL to the amplifier section 10. NMOS transistor 12 then starts conducting a predetermined operating current to ground. If the two differential input signals INP, INM are at the same voltage level, the operating current flow is divided equally between the two paths leading through NMOS transistors 11a and 11b, and the signal SN3 at node N3 has a level that allows PMOS transistor 21 to conduct a certain amount of current in the output section 20, bringing the output signal (OUT) to a certain level. If the level of differential input signal INP becomes higher than the level of differential input signal INM, the level of signal SN3 falls and the output signal (OUT) rises; if the level of differential input signal INP becomes lower than the level of differential input signal INM, the level of signal SN3 rises and the output signal (OUT) falls. The output voltage depends on the voltage difference between the differential input signals INP, INM.
FIG. 2 shows a waveform diagram illustrating the operation of the differential amplifier in FIG. 1 at a standby-to-active transition, illustrating the case in which the differential input signals INP, INM are both held at the VDD level in the standby state.
In the standby state, the enable signal EN is low (L), the signal SN3 at node N3 is pulled up to the power supply potential VDD, the differential input signals INP, INM are also at the VDD level, and NMOS transistor 12 is switched off. In this state, the potential SN1 at node N1 is pulled up to VDD-Vtn, where Vtn is the threshold voltage of NMOS transistors 11a, 11b. The source and body potential VB11 of NMOS transistors 11a, 11b is also pulled up to VDD-Vtn.
When the enable signal EN goes high (H), the differential input signals INP, INM fall to externally determined levels. If, for example, INP goes to a lower level than INM (INP<INM), the potential SN1 at node N1 falls to INM-Vtn. The bodies of NMOS transistors 11a, 11b also discharge to this potential, but since the discharge takes place gradually through the P+ regions in NMOS transistors 11a, 11b, the body potential VB11 takes time to reach the source level (SN1) at node N1.
During the period in which the source level differs from the body level in NMOS transistors 11a, 11b, the drain current characteristics of NMOS transistors 11a, 11b vary due to substrate effects. In general, when the body potential is higher than the source potential, the threshold voltage drops, the drain current increases, and the output signal level (OUT) no longer depends properly on the voltage difference between the differential input signals INP, INM.
If dimensional differences exist between NMOS transistors 11a, 11b, they cause a particular problem because the size of the substrate effect differs, destroying the balance in the differential amplifier circuit. Because the gate-source voltages VGS of NMOS transistors 11a, 11b operate near the threshold voltage Vtn, when the potential difference between the differential input signals INP, INM is small, as the substrate effect alters the transistor characteristics, it may also reverse the size relationship between the drain currents, resulting in a false output signal (OUT) as shown in FIG. 2.